1. Field of the Invention
The present invention relates to signal processing apparatuses, and more particularly to a signal processing apparatus in which a received signal or a signal reproduced from a recording medium is subjected to both adaptive equalization and sampling.
2. Description of the Background Art
In hard disk drives and magnetic tape drives where digital data is recorded/reproduced, a PRML (Partial Response Maximum Likelihood) method has been recently applied to detect data. In this method, a reproduced signal is first subjected to partial response equalization and then to maximum likelihood decoding by going through a Viterbi decoder, for example. For data detection under this PRML method, the drive needs to have two functions: a waveform equalization function of accurately subjecting a reproduced signal to partial response equalization; and a function of generating a clock signal which is accurately synchronized with reproduced data for sampling. A description is given next below about a reproduced signal processing part of a conventional hard disk drive applying the PRML method therein.
FIG. 8 is a block diagram showing the structure of a conventional signal processing apparatus used as the reproduced signal processing part of the hard disk drive. In FIG. 8, a reproduced signal 1 reproduced from a magnetic recording medium is subjected to partial response equalization in an analog equalizer 2. The equalized signal is subjected to sampling and digitalization in an AD converter (ADC) 3 with timing of a clock signal 15, and then is outputted as a sampled signal 4. The sampled signal 4 is provided to both an adaptive equalizer 5 and a phase error detector 9. The adaptive equalizer 5 adaptively corrects the sampled signal 4, depending on a state of the signal, in such a manner as to minimize a deviation from an ideal signal value caused by time-varying change in characteristics of the recording medium or reproduction head, for example, and then outputs an equalized signal 6. A Viterbi decoder 7 subjects, in consideration of partial response signal correlation, the equalized signal 6 to most likelihood decoding according to Viterbi algorithm, and then detects digital information previously recorded on the recording medium for output as reproduced data 8.
The phase error detector 9 detects, according to the sampled signal 4, any deviation of the sample point thereof from an ideal sample point (hereinafter, referred to as phase error). The phase error is resulted from the timing of sampling carried out in the AD converter 3, and the phase error detector 9 outputs a phase error signal 10. Note that, an exemplary structure of the phase error detector 9 is found in Roy. D. Cideciyan, et al., xe2x80x9cA PRML System for Digital Magnetic Recordingxe2x80x9d, IEEE Journal on selected areas in Communications, Vol. 10, No. 1, pp. 38-pp. 56 (January. 1992). The phase error signal 10 is converted into an analog signal in a DA converter (DAC) 11, and the analog signal is subjected to smoothing in a loop filter 12 to be an oscillation frequency control signal 13. A variable frequency oscillation circuit 14 oscillates in a frequency corresponding to a voltage of the oscillation frequency control signal 13,.and outputs the clock signal 15. The clock signal 15 is fed back as a clock for sampling in the AD converter 3. Since all of the AD converter 3, the phase error detector 9, the DA converter 11, the loop filter 12, and the variable frequency oscillation circuit 14 structure a PLL (Phase Locked Loop) circuit, the clock signal 15 can be a clock phase-locked to the reproduced data.
With such structure and operation, the conventional signal processing apparatus in FIG. 8 implements data reproduction under the PRML method.
Reproduced signal processing under such PRML method is found in, for example, J. D. Cocker, et al., xe2x80x9cImplementation of PRML in a rigid disk drivexe2x80x9d, IEEE Transactions on Magnetics, Vol. 27, No. 6 (November 1991).
As described in the foregoing, the conventional signal processing apparatus in FIG. 8 so generates the clock signal 15 as to minimize the phase error of the sample point of the sampled signal 4. From a viewpoint of implementing data reproduction with a lower error rate under the PRML method, it is preferable to so generate the clock signal 15 as to minimize the phase error of a sample point of the equalized signal 6. In this manner, the clock signal 15 can be more-accurately phase-locked to reproduced data.
Further, in the conventional signal processing apparatus in FIG. 8, the analog equalizer 2 is the one which mainly carries out the partial response equalization. However, from viewpoints of improving the degree of accuracy in equalization and simplifying the process of LSI, it is more preferable to carry out the equalization in digital processing.
With such viewpoints, the signal processing apparatus may be structured as shown in FIG. 9.
FIG. 9 is a block diagram showing the structure of the signal processing apparatus as an exemplary betterment for the conventional one in FIG. 8. In FIG. 9, any constituent found in FIG. 8 is denoted by the same reference numeral. Differences between these two signal processing apparatuses lie in three respects: the reproduced signal 1 skips the analog equalizer 2 and goes straight to an AD converter 17; an adaptive equalizer 80 subjects a sampled signal 33 to partial response equalization and also to adaptive equalization in such a manner as to minimize the equalization error; and a signal forwarded to the phase error detector 9 is the equalized signal 6. Such structure realizes data reproduction under the PRML method at a lower error rate, improvement in equalization accuracy, and a simplified LSI.
In the signal processing apparatus in FIG. 9, however, some competitive problem may be caused by two types of feed back control including adaptive equalization and PLL. Such new problem is described next below by referring to FIGS. 10 and 11.
FIG. 10 is a block diagram showing the structure of the adaptive equalizer 80 of the signal processing apparatus in FIG. 9. As shown in FIG. 10, the adaptive equalizer 80 is structured by a transversal-type filter with 5 taps and an adaptive controller 28. The sampled signal 33 is sequentially delayed by going through delay circuits 18 to 21, which each delays the signal on a data period basis. A coefficient circuit 22 multiplies the sampled signal 33 by a coefficient C(xe2x88x922) and other coefficient circuits 23 to 26 multiply outputs from the delay circuits 18 to 21, respectively, by coefficients C(xe2x88x921), C(0), C(1), and C(2) for output. An adding circuit 27 adds every output from the coefficient circuits 22 to 26, and then outputs the sum as the equalized signal 6. According to the equalized signal 6, the adaptive controller 28 adaptively controls every coefficient by tap coefficient signals 29a to 29e in such a manner as to minimize a mean-square error of the signal amplitude of the equalized signal 6. Such adaptive control is well known as an LMS (Least Means Square) algorithm, and is not described in detail.
The equalized signal 6 generated in the adaptive equalizer 80 is provided both to the Viterbi decoder 7 and the phase error detector 9. The phase error detector 9 detects any phase error of the sample point of the equalized signal 6, and then generates the phase error signal 10. From then onward, the clock signal 15 is generated according to the phase error signal 10 in a similar manner to the signal processing apparatus in FIG. 8, and is fed back to the AD converter 17 as a clock for sampling.
By referring to FIG. 11, it is described how the phase of the sample point of the equalized signal 6 is shifted by such operation. In FIG. 11, a linear line 31 shows the relationship between the phase of the sample point of the equalized signal 6 and the phase error indicated by the phase error signal 10 generated in the phase error detector 9. Herein, when the phase error indicated by the phase error signal 10 is 0, the phase of the equalized signal 6 is equal to a phase P1. Through the operation of the PLL, the phase of the sample point of the equalized signal 6 is controlled to be P1. A curve 32 shows the relationship between the phase of the sample point of the equalized signal 6 and the mean-square error of the signal amplitude of the equalized signal 6. The mean-square error is an evaluation function of tap control in the adaptive equalizer 80, and each tap coefficient therein is so controlled as to minimize the mean-square error. Herein, when the mean-square error is minimum, the phase of the equalized signal 6 is equal to a phase P2. Through the adaptive equalization carried out in the adaptive equalizer 80, the phase of the sample point of the equalized signal 6 is controlled to be P2. Note herein that, the phases P1 and P2 coincide with each other under ideal conditions. In reality, however, the coincidence is not achieved but a slight difference is observed therebetween. This is because, some distortion or noise is observed in the equalized signal 6, and a phase error detection characteristic of the phase error detector 9 is not necessarily ideal.
In the state shown in FIG. 11, it is assumed that the phase of the sample point of the equalized signal 6 is on the phase P1. If this is the case, the adaptive equalizer 80 controls the tap coefficients in such a manner as to minimize the mean-square error of the equalized signal 6, that is, as to bring the phase of the sample point thereof closer to the phase P2. In detail, in the adaptive equalizer 80 in FIG. 10, the coefficients C(xe2x88x921) and C(xe2x88x922) of the coefficient circuits 23 and 22 are more weighted (i.e., absolute value increased), while the coefficients C(1) and C(2) of the coefficient circuits 25 and 26 are less weighted. As a result, the phase of the sample point of the equalized signal 6 slightly moves from P1 to the direction of P2.
Consequently, the phase of the sample point of the equalized signal 6 is displaced from P1, and accordingly the value of the phase error signal 10 detected in the phase error detector 9 is not 0 any more. Therefore, by the operation of the PLL, oscillation phase of the clock signal 15 is so controlled as to bring the phase of the sample point of the equalized signal 6 back to P1 again.
Thereafter, the adaptive equalizer 80 again so controls the tap coefficients as to bring the phase of the sample point of the equalized signal 6 closer to P2, and consequently the tap coefficients C(xe2x88x921) and C(xe2x88x922) are weighted still more, while the tap coefficients C(1) and C(2) are weighted still less. The phase of the sample point of the equalized signal 6 thus slightly moves from P1 to the direction of P2 again.
If such operation is repeated, a center of weight of the tap coefficients in the adaptive equalizer 80 keeps moving from the coefficient C(0) of the coefficient circuit 24 to the coefficient C(xe2x88x921) of the coefficient circuit 23 and the coefficient C(xe2x88x922) of the coefficient circuit 22. Note that, xe2x80x9ccenter of weight of the tap coefficientsxe2x80x9d herein means xe2x80x9cideational center of weightxe2x80x9d where a plurality of tap coefficients show a well-balance. As a result, the 5-tap adaptive equalizer 80 eventually becomes beyond control and cannot fully carry out the equalization processing any more, thereby rendering the error rate increased.
As is known from the above, if the signal processing part is structured as in FIG. 9 for the purpose of decreasing the error rate, the PLL for generating the clock signal 15 and the adaptive equalizer 80 may compete in operation with each other, and accordingly the adaptive equalizer 80 fails to fully carry out the adaptive equalization processing and the error rate is increased.
Therefore, an object of the present invention is to provide a signal processing apparatus in which accurate phase lock is implemented by generating a clock signal after any phase error being detected from an adaptively-equalized signal, and also phase-lock processing and adaptive-equalization processing do not compete in operation with each other, thereby preventing an equalization characteristic from being deteriorated.
The present invention has the following features to attain the object above.
A first aspect of the present invention is directed to a signal processing apparatus, comprising:
a sampling part for subjecting an incoming signal to sampling with a given clock signal;
an equalization part for subjecting the signal sampled by the sampling part to product-sum operation according to a plurality of tap coefficients;
an adaptive control part for setting, on the basis of an output signal from the equalization part, a plurality of tap coefficients of said equalization part according to a given algorithm;
a phase error detection part for detecting a phase error from the output signal from the equalization part;
a tap barycenter detection part for detecting, according to the plurality of tap coefficients set by the adaptive control part, a barycenter of the tap coefficients;
a phase shift part for correcting an output from the phase error detection part according to an output from the tap barycenter detection part; and
an oscillation part for oscillating in a frequency based on an output signal from the phase shift part, and generating the given clock signal for output to the sampling part.
As described above, in the first aspect, accurate phase-lock is realized by carrying out phase-lock according to an adaptively-equalized signal, deterioration of an equalization characteristic which has been resulted from competition in operation between phase lock processing and adaptive equalization processing is prevented by controlling movement of a barycenter of tap coefficients to be within a given range, and improvement in equalization accuracy and a simplified LSI are achieved by digital equalization processing.
According to a second aspect, in the first aspect,
the tap barycenter detection part includes a product-sum operation part for multiplying, by a given value, every absolute value of the tap coefficients set by the adaptive control part, and adding the values.
As described above, in the second aspect, with simple structure and operation, the barycenter of the tap coefficients is easily determined according to a plurality of tap coefficients.
According to a third aspect, in the first aspect, the phase shift part selects any one of correction values predetermined according to the output from the tap barycenter detection part, and correcting the output from the phase error detection part according to the selected correction value.
As described above, in the third aspect, with simple structure and operation, correction can be greatly effective.
A fourth aspect is directed to a signal processing apparatus, comprising:
an equalization part for subjecting an incoming signal to product-sum operation according to a plurality of tap coefficients;
a sampling part for subjecting an output signal from the equalization part to sampling with a given clock signal;
an adaptive control part for setting, on the basis of an output signal from the sampling part, a plurality of tap coefficients of the equalization part according to a given algorithm;
a phase error detection part for detecting a phase error from the output signal from the sampling part;
a tap barycenter detection part for detecting, according to the plurality of tap coefficients set by the adaptive control part, a barycenter of the tap coefficients;
a phase shift part for correcting an output from the phase error detection mean according to an output from the tap barycenter detection part; and
an oscillation part for oscillating in a frequency according to an output signal from the phase shift part, and generating the given clock signal for output to the sampling part.
As described above, in the fourth aspect, accurate phase-lock is realized by carrying out phase-lock according to an adaptively-equalized signal, deterioration of an equalization characteristic which has been resulted from competition in operation between phase lock processing and adaptive equalization processing is prevented by controlling movement of a barycenter of tap coefficients to be within a given range, and response in the phase lock process can be made more quickly thanks to shorter delay time in the PLL loop.
According to a fifth aspect, in the fourth aspect, the tap barycenter detection part includes an operation part for multiplying, by a given value, every absolute value of the tap coefficients set by the adaptive control part, and adding the values.
As described above, in the fifth aspect, with simple structure and operation, the barycenter of the tap coefficients is easily determined according to a plurality of tap coefficients.
According to a sixth aspect, in the fourth aspect,
wherein the phase shift part selects any one of correction values predetermined according to the output from the tap barycenter detection part, and correcting the output from the phase error detection part according to the selected correction value.
As described above, in the sixth aspect, with simple structure and operation, correction can be greatly effective.